University of Minnesota
Computer Engineering
Research Group

Dr. Matthew O'Keefe


DLX Instructions as described in

Computer Architecture: A Quantitative Approach, Second Edition

by
David A. Patterson and John L. Hennessey


Note: all instructions below have been implemented with the execption of RFE

Instruction type/opcode Instruction meaning
Data transfers Move data between registers and memory, or between the integer and FP or special registers; only memory address mode is 16-bit displacement + contents of an integer register
LB, LBU, SB Load byte, load byte unsigned, store byte
LH, LHU, SH Load halfword, load halfword unsigned, store halfword
LW, SW Load word, store word
LF, LD, SF, SD Load single precision float, load double precision float, store single precision float, store double precision float
MOVI2S, MOVS2I Move from/to integer register to/from a special register
MOVF, MOVD Copy one floating point register or a DP pair to another register or pair
MOVFP2I, MOVI2FP Move 32 bits from/to a FP register to/from an integer register
Arithmetic, logical Operations on integer or logical data in integer registers; signed arithmetic instructions trap on overflow
ADD, ADDI, ADDU, ADDUI Add, add immediate (all immediates are 16 bits); signed and unsigned
SUB, SUBI, SUBU, SUBUI Subtract, subtract immediate; signed and unsigned
MULT, MULTU, DIV, DIVU Multiply and divide, signed and unsigned; operands must be floating-point registers; all operations take and yield 32-bit values
AND, ANDI And, and immediate
OR, ORI, XOR, XORI Inclusive or, Inclusive or immediate, exclusive or, exclusive or immediate
LHI Load high immediate - loads upper 16 bits of register with immediate and zeros the lower 16 bits
SLL, SRL, SRA,
SLLI, SRLI, SRAI
Shifts; both immediate (S__I) and variable form (S__); shifts are left logical, right logical and right arithmetic
SEQ, SNE, SLT,
SGT, SLE, SGE
Set conditional; set equal zero, set not equal zero, set less than, set greater than, set less than or equal, set greater than or equal
Control Conditional branches and jumps; PC-relative or through register
BEQZ, BNEZ Branch integer register equal/not equal to zero; 16 bit offset from PC+4
BFPF, BFPT Test comparison bit in the FP status register and branch; 16 bit offset from PC+4
J, JR Jumps; 26 bit offset from PC+4 (J) or target register (JR)
JAL, JALR Jump and link; save PC+8 to R31, target is 26 bit offset from PC+4 (JAL) or a register (JALR)
TRAP Transfer to operating system at a vectored address
RFE Return to user code from an exception; restore user mode
Floating point Floating-point operations on DP and SP floats
ADDD, ADDF Add DP and SP floats
SUBD, SUBF Subtract DP and SP floats
MULTD, MULTF Multiply DP and SP floats
DIVD, DIVF Divide DP and SP floats
CVTD2F, CVTD2I,
CVTF2D, CVTF2I,
CVTI2D, CVTI2F
Convert instructions; CVTx2y converts from type x to type y, where x and y are one of D (double precision float), F (single precision float) or I (integer); both operands are in floating point registers
EQD, EQF, NED, NEF, LTD, LTF,
GTD, GTF, LED, LEF, GED, GEF
DP and SP compares; set comparison bit in FP status register

Computer Engineering
Department of Electrical Engineering
University of Minnesota